1. Field of the Invention
The present invention relates to a transistor technology. In particular, the present invention relates to a field-effect transistor, a method of manufacturing the same, a semiconductor device and a semiconductor memory device having the field-effect transistor.
2. Description of the Related Art
Incident radiation (cosmic ray, thermal neutron, α-ray and so on) into a semiconductor memory device generates electron-hole pairs due to collision with a silicon substrate. The generated electron-hole pairs are collected in a diffusion layer, which causes a change in potential at a node. What most contributes to the potential change at the node is funneling immediately under a drain region among charge collection mechanisms. A phenomenon that a memory cell data is rewritten due to the potential change at the node is called a “soft error”. With the advance of miniaturization of a device in recent years, the influence of electrons and holes caused by the radiation becomes more conspicuous.
Japanese Laid Open Patent Application JP-P2000-12547A discloses a technique whose object is to enhance resistance to a single event upset (the soft error). According to a semiconductor device disclosed in the patent document, a high-density defect layer is formed in a source region and a region immediately under a drain depletion layer below a drain region. The high-density defect layer functions as a recombination center and facilitates recombination of minority carriers.
As a general technique, a vertical field-effect transistor is disclosed in Japanese Laid Open Patent Application JP-A-Heisei 5-198817 and Japanese Laid Open Patent Application JP-P2002-26279A. In the vertical field-effect transistor, a moving direction of carriers (a conduction direction) is perpendicular to a surface of a substrate.
A document; T. Sato et al., “SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications”, IEEE, IEDM 01-809, 37.1.1-37.1.4, 2001, discloses a SON (Silicon on Nothing) MOS transistor whose object is to improve performance. The SON-MOS transistor is manufactured based on an ESS (Empty Space in Silicon) technique. According to the SON-MOS transistor disclosed in the document, a gate electrode is formed on a substrate and an ESS structure is formed below a channel region.